The overall trend of the chip, divided long will be together, together will be divided
Romance of the Three Kingdoms, the first time on the opening statement: "That is to say that the world trend, divided for a long time will be united, united for a long time will be divided. This sentence can be used to describe a chip technology is also a very apt.
Chip early is a single function chip, evolved to multi-function multi-chip package (multi-chip module; MCM), to the system on a chip (system on a chip; SoC), system in a package (system in a package; SiP), and even to the recent commonly known as small chip (chiplet). These points together along the way, with the semiconductor process and packaging and testing technology, and even the system side of the application are inextricably linked.
In the early days of system applications, various ICs with different functions were integrated together in the form of printed circuit boards. However, with the increasing frequency of operation required by the system side, as well as the requirement of reducing the size, the integration of several core ICs into the same package to shorten the transmission distance between each other has become a trend, and the multi-chip packaging technology (MCM) has emerged. In addition, SiP, heterogeneous integration, and even 3DIC, are more advanced packaging methods, the technology includes the stacking of chips. In short,wafer test if the chip design or wafer production process cannot meet the needs of the system side, it will seek to provide a solution in the package. Therefore, chip design, wafer fabrication and packaging and testing is a three-pronged approach, and each other with time and technological evolution of each other.
Known Good Die (KGD) is a major challenge in multi-chip packaging, usually a chip must be packaged to do a complete test before shipment. But with many bare crystals, not being sure that every single one is good can lead to significant yield losses. In order to ensure that every piece of bare crystal is a good crystal, the wafer has developed chip probes, including cutting-edge probe cards and test equipment, these products also form an important part of the whole industry chain.
With the development of wafer process control technology is more and more mature and progress, wafer level testingthe wafer fab has not only in the same set of processes, to provide a different social work to carry out the voltage or collapse voltage of the crystal. At the same time, by playing a very important role in the impact of embedded memory, such as flash memory (Flash), EEPROM, OTM (one time memory), can also be realized one by one for the same wafer. So far, we have combined logic analysis operations, analog electronic circuits, memory, and even high-voltage equipment power supply enterprise management, system single-chip architecture design can finally be integrated and can be realized in a concrete way.
Apple's M1 chip technology can be said to be the ultimate in our current management system single chip, integrating the Arm architecture of the CPU, GPU, AI neural acceleration through the network development engine, as well as social links to these data units in China fabric sink interface. Compared to the x86 architecture, the M1 chip needs to have the advantages of high performance, low power consumption and high integration, the M1 Max contains 57 billion crystals in a common chip, which is currently the leading control chip for personal use computers.
Another extreme system-on-a-chip is NVIDIA's graphics processor, the latest generation of NVIDIA's Hopper graphics processor, which contains 80 billion transistors, 15,000 cores, and uses a 4-nanometer TSI process, with each chip nearly 3 centimeters in length and width. Giant chips directly challenge fab yields and subsequent package testing,failure analysis and affect the area of each 12-inch wafer that can be used efficiently. Assuming that the demand for supercomputer (HPC) chips on the system continues to grow, it will be necessary to start cutting back moderately when the area of individual chips cannot be increased any further, which is why smaller chips are proposed.
It's worth noting that NVIDIA GPUs have always been named using the surnames of famous scientists, such as Ampere, Volt, and Pascal. This time, Hopper, a famous American female computer expert who worshipped Major Generals, and her name, Grace, were named for NVIDIA's first commercially available CPU.
The chip not only solves the problem of increasing the chip area, but also allows different functional blocks in a single chip to be partitioned to realize different process conditions. For example, the core of the chip is to achieve 5nm, and the convergence of its I/O or master parts can be achieved using a more mature process to further optimize costs. Therefore, the transfer protocol between multiple chips is very important, which is the interface standard UCIE (Universal Chiplet Interconnect Express). In effect, this is the realization of heterogeneous integration, in other words, the SOC Advanced System-on-Chip (SOIC).
In this chip separation and integration of the general trend, a fledgling chip design company in the opposite direction, the entire 12-inch wafer into a side length of more than 20 centimeters, transistors 1.2 trillion single high-speed computing chip. The reason is that in the future the chip transmits one bit more energy than is lost in calculating one bit, and this design can increase the frequency of operations. Whether this approach will lead the way remains to be seen.
The 18-inch wafer program, which made a lot of noise more than a decade ago but was stillborn, has recently been brought up again by people who can cope with the increasingly large single chips. It seems that China's semiconductor R&D staff has been constantly challenged to analyze problems and research as well as students to come up with their own solutions to these problems, and have been able to continue to move forward on the path of division and integration.
